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Products & Services Telemetry & Communications

Multi-disciplined switches for flight test instrumentation networks

Paige SmithBy Paige Smith16th March 20212 Mins Read
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A range of products with a multi-disciplined architecture that provide complementary capabilities with significant performance improvements over legacy hardware
A range of products with a multi-disciplined architecture that provide complementary capabilities with significant performance improvements over legacy hardware

Integrated Switch & Gateway Units benefit budgets by decreasing box counts, reducing integration efforts, benefiting SWaP (Size, Weight and Power) and constrained implementations all while increasing overall system capabilities.

In test network implementations, switches were typically single-purpose units for switching and routing Ethernet traffic.  In the case of managed switches, the user could implement traffic policing policies, setup Virtual Local Area Networks (VLAN’s) and assign traffic priorities among other management functions.

The integrated Ethernet Switch (iES) not only provides layer 2/3 switch management but also adds a Global Positioning System (GPS) receiver, independent hardware-based IEEE-1588 time engines with Grand Master capability and IRIG Time Code Generation (TCG). Data driven and user commanded discrete outputs, and Pulse Code Modulation (PCM) serial inputs/outputs extend the capability of the switch. The iES includes an FPGA interface, tied directly to the switch fabric, providing content level data filtering and processing across the switch ports. The result of this content filtering and processing is sending end-results to network destinations and / or telemetering a merged data sub-set via PCM (eiher Chapter 4 or 7) or ISO / IEC 13239 High-Level Data Link
Control (HDLC). 

For smaller applications with similar requirements, the instrumentation Gateway Unit (iGU) provides Ethernet interfaces with network timing, PCM input/output and a layer 2/3 managed switch. An integrated FPGA and CPU providing a wide array of capability in a single compact unit.

The FPGA and CPU provide real-time data processing, conversion or translation tasks including IRIG 106 Chapter 10 publishing, Ethernet to IRIG 106 Chapter 7 PCM or HDLC output. This allows a user to combine sources of data and convert it to Chapter 10 while sending to a recorder over Ethernet and outputting PCM to a transmitter for telemetering of that data.  

This multi-disciplined approach helps to meet the requirements of many projects, air, land and at sea. Recently the iES and iGU were used in an unmanned maritime application where they converted PCM streams to CH10 and provided an Ethernet link to a dedicated recorder.

This article was provided by Telspan

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Paige Smith

Paige is an experienced journalist and editor who started her career covering the building and architecture sector. After several years writing and editing online and print articles for leading journals in this sector, she is bringing her thorough approach to technical content to covering the business aviation industry. In her spare time she enjoys traveling and is always planning her next trip.

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